arm: fix comment in HTCR setup.

Reported-by: Gihun Jung <gihun.jung@gmail.com>
Signed-off-by: Tim Deegan <tim@xen.org>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index db3baa0c25c30f91492ce01f9829a8166b158902..f2f581da9729631fed841f4374918f7135b92c50 100644 (file)
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -189,7 +189,7 @@ skip_bss:
 
         /* Set up the HTCR:
          * PT walks use Outer-Shareable accesses,
-         * PT walks are write-back, no-write-allocate in both cache levels,
+         * PT walks are write-back, write-allocate in both cache levels,
          * Full 32-bit address space goes through this table. */
         ldr   r0, =0x80002500
         mcr   CP32(r0, HTCR)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index b7ab251385a707ca3302d5501cb700e4f305434b..bbde419d5e5638d9a9b3f2a39b24efce85c8ed01 100644 (file)
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -173,7 +173,7 @@ skip_bss:
          * PASize -- 4G
          * Top byte is used
          * PT walks use Outer-Shareable accesses,
-         * PT walks are write-back, no-write-allocate in both cache levels,
+         * PT walks are write-back, write-allocate in both cache levels,
          * Full 64-bit address space goes through this table. */
         ldr   x0, =0x80802500
         msr   tcr_el2, x0